VHDL学习：二选一电路

代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux2 is
	port(d0:in std_logic_vector(3 downto 0);
		d1:in std_logic_vector(3 downto 0);
		sel:in std_logic;
		q:out std_logic_vector(3 downto 0));
end mux2;
architecture Behavioral of mux2 is
begin
	process(d0,d1,sel)
	begin
		if(sel='1') then
			q<=d0;
		else
			q<=d1;
		end if;
	end process;
end Behavioral;

仿真：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux2_bench is
--  Port ( );
end mux2_bench;
architecture Behavioral of mux2_bench is
	component mux2 port(d0:in std_logic_vector(3 downto 0);
		d1:in std_logic_vector(3 downto 0);
		sel:in std_logic;
		q:out std_logic_vector(3 downto 0));
	end component;
	signal d0:std_logic_vector(3 downto 0):="0110";
	signal d1:std_logic_vector(3 downto 0):="1001";
	signal sel:std_logic;
	signal q:std_logic_vector(3 downto 0);
begin
	dut:mux2 port map(d0,d1,sel,q);
	process
	begin
		sel<='0';
		wait for 10ns;
		sel<='1';
		wait for 10ns;
	end process;
end Behavioral;