VHDL学习：优先编码器

代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity my_1 is
--  Port ( );
port(input:in std_logic_vector(7 downto 0);
		y:out std_logic_vector(2 downto 0));
end my_1;
architecture Behavioral of my_1 is
begin
    process(input)
	begin
		if input(0)='0' then
			y<="111";
		elsif input(1)='0' then
			y<="110";
		elsif input(2)='0' then
			y<="101";
		elsif input(3)='0' then
			y<="100";
		elsif input(4)='0' then
			y<="011";
		elsif input(5)='0' then
			y<="010";
		elsif input(6)='0' then
			y<="001";
		else
			y<="000";
		end if;
	end process;
end Behavioral;

仿真：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity my_1_bench is
--  Port ( );
end my_1_bench;
architecture Behavioral of my_1_bench is
    signal input:std_logic_vector(7 downto 0):="00000000";
    signal y:std_logic_vector(2 downto 0):="000";
    component my_1
		port(input:in std_logic_vector(7 downto 0);
			y:out std_logic_vector(2 downto 0));
	end component my_1;
begin
    uut:my_1 port map(input, y);
	process
	begin
		wait for 10ns;
			input<="00000000";
		wait for 10ns;
			input<="00000001";
		wait for 10ns;
			input<="00000011";
		wait for 10ns;
			input<="00000111";	
		wait for 10ns;
			input<="00001111";
		wait for 10ns;
			input<="00011111";
		wait for 10ns;
			input<="00111111";
		wait for 10ns;
			input<="01111111";
	end process;
end Behavioral;