VHDL学习：D触发器

D触发器：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity my_test is
	port(clk,d:in std_logic;
		q:out std_logic);
--  Port ( );
end my_test;

architecture Behavioral of my_test is
begin
	process(clk)
	begin
		if(clk'event and clk='1')then
			q<=d;
		end if;
	end process;
end Behavioral;

仿真：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity my_test_bench is
--  Port ( );
end my_test_bench;

architecture Behavioral of my_test_bench is
	component my_test port(clk,d:in std_logic;
			q:out std_logic);
	end component;
	constant clk_period:time := 20ns;
	signal clk:std_logic:='0';
	signal d:std_logic:='0';
	signal q:std_logic:='0';
begin
	dut:my_test port map(clk,d,q);
	clk <= not clk after clk_period/2;
process
begin
	wait for clk_period;
	d<='0';
	wait for clk_period;
	d<='1';
end process;
end Behavioral;