VHDL学习：二分频器

代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;

entity M_LineTransClmn is
    Port 
    ( 
        CpSl_Clk_i                      : in  std_logic                         ;
        CpSl_Rst_iN                     : in  std_logic                         ;       
        CpSl_SumClk_o                   : out std_logic                         
    );
end M_LineTransClmn;

architecture Behavioral of M_LineTransClmn is
	signal PrSl_SumClk_s:std_logic;
begin
    process(CpSl_Clk_i, CpSl_Rst_iN) begin
		if (CpSl_Rst_iN = '0') then
			PrSl_SumClk_s <= '0';
		elsif rising_edge(CpSl_Clk_i) then        --使用rising_edge()判断上升沿
			PrSl_SumClk_s  <=  not  PrSl_SumClk_s;
		end if;
	end process;
	CpSl_SumClk_o <= PrSl_SumClk_s  ; 
end Behavioral;

仿真：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity M_LineTransClmn_Bench is
--  Port ( );
end M_LineTransClmn_Bench;

architecture Behavioral of M_LineTransClmn_Bench is
	component M_LineTransClmn
	Port 
    ( 
        CpSl_Clk_i                      : in  std_logic                         ;
        CpSl_Rst_iN                     : in  std_logic                         ;
        CpSl_SumClk_o                   : out std_logic                         
    );
	end component;
	signal    CpSl_Clk_i                : std_logic:='0';
	signal    CpSl_Rst_iN               : std_logic:='0';
	signal    CpSl_SumClk_o             : std_logic;
	constant  clk_period                : time:=20ns;
begin
	dut:M_LineTransClmn port map(CpSl_Clk_i, CpSl_Rst_iN, CpSl_SumClk_o);
	CpSl_Clk_i <= not CpSl_Clk_i after clk_period/2;
	process begin 
                wait for 20ns;
		CpSl_Rst_iN<='1';
		wait;
	end process;
end Behavioral;