VHDL学习：分频器

代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity frequency_divider is
    Port 
    ( 
            CpSl_Clk_i                      : in  std_logic                         ;
            CpSl_Rst_iN                     : in  std_logic                         ;
            CpSl_SumClk_2o                  : out std_logic                         ;
	    CpSl_SumClk_4o                  : out std_logic                         ;
	    CpSl_SumClk_8o                  : out std_logic                         ;
            CpSl_SumClk_16o                 : out std_logic                         
    );
end frequency_divider;

architecture Behavioral of frequency_divider is
    signal  PrSl_SumClk_s                   : std_logic_vector(3 downto 0);
begin
    process(CpSl_Clk_i, CpSl_Rst_iN) begin
        if (CpSl_Rst_iN = '0') then
            PrSl_SumClk_s                   <= "0000"                               ;
        elsif(CpSl_Clk_i'event and CpSl_Clk_i='1') then
            PrSl_SumClk_s                   <= PrSl_SumClk_s+1                      ;
        end if;
    end process;
    CpSl_SumClk_2o                          <= PrSl_SumClk_s(0)                     ;
    CpSl_SumClk_4o                          <= PrSl_SumClk_s(1)                     ;
    CpSl_SumClk_8o                          <= PrSl_SumClk_s(2)                     ;
    CpSl_SumClk_16o                         <= PrSl_SumClk_s(3)                     ;
end Behavioral;

仿真：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity frequency_divider_bench is
--  Port ( );
end frequency_divider_bench;

architecture Behavioral of frequency_divider_bench is
	component frequency_divider
		Port 
		( 
		    CpSl_Clk_i                      : in  std_logic                         ;
                    CpSl_Rst_iN                     : in  std_logic                         ;
                    CpSl_SumClk_2o                  : out std_logic                         ;
		    CpSl_SumClk_4o                  : out std_logic                         ;
		    CpSl_SumClk_8o                  : out std_logic                         ;
		    CpSl_SumClk_16o                 : out std_logic                         
		);
	end component;
	signal    CpSl_Clk_i                    : std_logic:='0';
	signal    CpSl_Rst_iN                   : std_logic:='0';
	signal    CpSl_SumClk_2o                : std_logic;
	signal    CpSl_SumClk_4o                : std_logic;
	signal    CpSl_SumClk_8o                : std_logic;
	signal    CpSl_SumClk_16o               : std_logic;
	constant  clk_period                    : time:=20ns;
begin
	dut:frequency_divider port map(CpSl_Clk_i, CpSl_Rst_iN, CpSl_SumClk_2o, CpSl_SumClk_4o, CpSl_SumClk_8o, CpSl_SumClk_16o);
	CpSl_Clk_i <= not CpSl_Clk_i after clk_period/2;
	process begin 
                wait for 20ns;
		CpSl_Rst_iN<='1';
		wait;
	end process;
end Behavioral;