VHDL学习：计数器

代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
	port(clk:in std_logic;
		reset:in std_logic;
		count:out std_logic_vector(3 downto 0)
        );
end counter;

architecture Behavioral of counter is
    signal temp:std_logic_vector(3 downto 0);
begin
    process(clk,reset)
    begin
	if(reset='1') then
		temp<="0000";
	elsif(clk'event and clk='1') then
		temp <= temp + 1;
	end if;
    end process;
    count<=temp;
end Behavioral;

仿真：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity counter_bench is
--  Port ( );
end counter_bench;
architecture Behavioral of counter_bench is
	component counter
	port(clk:in std_logic;
		reset:in std_logic;
		count:out std_logic_vector(3 downto 0));
	end component;
	constant clk_period:time:=20ns;
	signal clk:std_logic:='0';
	signal reset:std_logic:='0';
	signal count:std_logic_vector(3 downto 0);
begin
	dut:counter
	port map(clk,reset,count);
	clk<=not clk after clk_period/2;
	process
	begin
		wait for 20ns;
		reset<='1';
		wait for 20ns;
		reset<='0';
		wait for 300ns;
	end process;
end Behavioral;